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EZ80F915050MOD
eZ80F91 Module
Product Specification
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ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
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532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
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Document Disclaimer
(c) 2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Revision History
Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document Revision Level Section 10 Page # All 12
Date July 2004
Description
Formatted to current publication standards Ethernet PHY and RJ45 Connector section Bill of Materials for the eZ80F91 Module Part number change to AMD MII.
Part number change to internal crystal at jumper location Y3.
22
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi The eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 eZ80F91 Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet PHY and RJ45 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fast Buffer (U10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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List of Figures
Figure 1. eZ80F91 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3 Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration--JP1 4 Figure 3. eZ80F91 Module I/O Connector Pin Configuration--JP2 . . . . . . . . . 8 Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature . 15 Figure 5. Physical Dimensions of the eZ80F91 Module . . . . . . . . . . . . . . . . . 18 Figure 6. eZ80F91 Module--Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. eZ80F91 Module--Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3--Connectors and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3--CPU and PHY . . . 26 Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3--Module Memory . . 27
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List of Tables
Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* . . . . . . . 5 Table 3. eZ80F91 Module I/O Connector Pin Identification* . . . . . . . . . . . . . . . . 8 Table 4. eZ80F91 Ethernet Module MII Resistor Configuration . . . . . . . . . . . . . 12 Table 5. Flash Memory Programming Signals and Jumpers . . . . . . . . . . . . . . . 16 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Bill of Materials for the eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . 22
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The eZ80F91 Module
The eZ80F91 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity. This expandable module is powered by ZiLOG's latest power-efficient, highspeed, optimized pipeline architecture eZ80F91 microcontroller, a member of ZILOG's family of eZ80Acclaim! Flash Microcontrollers. The eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which can operate with a clock speed of 50 MHz. It can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F91 Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications.
Module Features * * * * * * * * * * * * *
Factory-default operating clock frequency at 50 MHz 10/100 Base-T Ethernet PHY with RJ45 connector 512 KB fast SRAM 256 KB on-chip Flash memory 1 MB off-chip NOR Flash memory Battery-backed Real-Time Clock I/O connector provides 32 general-purpose 5 V-tolerant I/O pinouts ZiLOG's industry-leading IrDA transceiver--ZiLOG ZHX1810 Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data) Low-cost connection to carrier board via two 2x30pin headers Small footprint 63.5mm x 78.7mm 3.3 V power supply Standard operating temperature range: 0C to +70C
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eZ80F91 Controller Features * * * * * * * * * * * * * * * * * * *
The eZ80F91 device contains 256 KB of Flash memory and 8 KB of SRAM Single-cycle instruction fetch, high-performance, pipelined eZ80(R) CPU core 10/100 Mbps Ethernet MAC with 8KB frame buffer Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control Two UARTs with independent baud rate generators and support for 9-bit operation SPI with independent clock generator I2C with independent clock generator Infrared Data Association (IrDA)-compliant infrared encoder/decoder New DMA-like eZ80(R) instructions for efficient block data transfer External interface with 4 chip selects, individual wait state generators, and an external WAIT input pin -- supports Intel- and Motorola-style buses Flexible-priority vectored interrupts (both internal and external) and interrupt controller Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup Four 16-bit Counter/Timers with prescalers and direct input/output drive Watch-Dog Timer 32 bits of general-purpose I/O JTAG and ZDI debug interfaces 144-pin LQFP package 3.0-3.6 V supply voltage with 5V tolerant inputs Standard operating temperature range: 0C to +70C
Block Diagram
Figure 1 provides a block diagram of the eZ80F91 Module.
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Figure 1. eZ80F91 Module Functional Block Diagram
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Pin Description
Peripheral Bus Connector
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of the eZ80F91 Module. The eZ80(R) Development Platform, however, features a 50pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP1 connector to pin 50 of the eZ80(R) Development Platform's JP1 connector so that pins 1-10 of the eZ80F91 Module overlap the edge of the eZ80(R) Development Platform. Table 2 identifies the pins and their functions.
Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration--JP1
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Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low.
Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* Pull Up/Down*
Pin # 1 2 3 4 5 6 7
Symbol Reserved Reserved Reserved Reserved TRSTN Reserved F91_WE
Signal Direction Comments
Input
Reset for On-Chip Instrumentation (OCI).
PU 10 K
Input
A Low enables a Write to on-chip Flash memory. If this pin is unconnected, on-chip Flash memory is write-protected.
8 9 10 11 12 13 14 15 16 17 18 19 20 21
Reserved GND VCC A6 A0 A10 A3 GND VCC A8 A7 A13 A9 A15 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). 3.3 V supply input pin. VSS/Ground (0 V). 3.3 V supply input pin.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down*
Pin # 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Symbol A14 A18 A16 A19 GND A2 A1 A11 A12 A4 A20 A5 A17 Reserved DIS_Flash
Signal Direction Comments Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
PU 10 K
Input
A Low disables onboard Flash memory. Flash is enabled if DIS_Flash is not connected; CMOS Input 3.3 V (5 V tolerant).
37 38 39 40 41 42 43 44 45
A21 VCC A22 A23 CS0 CS1 CS2 D0 D1 PU 4k PU 4k
Bidirectional 3.3 V supply input pin. Bidirectional Bidirectional Output Output Output Bidirectional Bidirectional
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down* PU 4k PU 4k PU 4k PU 4k
Pin # 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol D2 D3 D4 D5 GND D7 D6 MREQ IORQ GND RD WR INSTRD BUSACK BUSREQ
Signal Direction Comments Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V).
PU 4k
Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Output Output
PU 2k
Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
I/O Connector
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80F91 Module. The eZ80(R) Development Platform, however, features a 50-pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP2 connector to pin 50 of the eZ80(R) Development Platform's JP2 connector so that pins 1-10 of the eZ80F91 Module overlap the edge of the eZ80(R) Development Platform. Table 3 identifies the pins and their functions.
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Figure 3. eZ80F91 Module I/O Connector Pin Configuration--JP2 Table 3. eZ80F91 Module I/O Connector Pin Identification* Pull Up/Down Signal Direction Bidirectional Bidirectional Bidirectional Bidirectional
Pin # 1 2 3 4
Symbol PA7 PA6 PA5 PA4
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Bidirectional Bidirectional Bidirectional Bidirectional 3.3 V supply input pin. VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional VSS/Ground (0 V). Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Pin # 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Symbol PA3 PA2 PA1 PA0 VCC GND PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction
Pin # 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Symbol GND PD5 PD4 PD3 PD2 PD1 PD0 TDO TDI/ZDA GND TRIGOUT TCK/ZCL TMS RTC_VDD
Comments VSS/Ground (0 V).
Bidirectional PD 4k Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Input JTAG Data Output pin. JTAG Data Input pin. VSS/Ground (0 V). Output PU 10 K Input PU 10 K Input Active High trigger event indicator. JTAG Input. High on reset enables ZDI mode; Low on reset enables OCI debug. JTAG Test Mode Select Input. RTC supply. For proper operation of the eZ80F91 Module, this pin must be connected to the same power source that powers the module (as is done on the ZiLOG development platform). Output PU 4k Bidirectional Synchronous CPU clock output. I2C Bus Clock. VSS/Ground (0 V). PU 4k Bidirectional Power PU 10 K Input I2C Data Clock. VSS/Ground (0 V). A Low enables a Write to external Flash memory boot block area. If this pin is unconnected, the Flash memory boot block area is write-protected. VSS/Ground (0 V).
44 45 46 47 48 49
EZ80CLK I2CSCL GND I2CSDA GND FlashWE
50
GND
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Output PU 10 K Input PU 2k PU 2k Bidirectional Input
Pin # 51 52 53 54
Symbol CS3 DIS_IRDA RESET WAIT
Comments Used on the eZ80190, eZ80L92, eZ80F92, eZ80F93 devices and connected to the CS8900 EMAC. A Low disables the onboard IRDA transceiver to use PC0/PC1 UART pins externally. Reset Output from module or push-button reset. Driving the WAIT pin Low forces the CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 3.3 V supply input pin. VSS/Ground (0 V).
55 56 57
VCC GND HALT_SLP
Output, Active A Low on this pin indicates that the CPU enters either Low HALT or SLEEP mode because of execution of either a HALT or SLP instruction. PU 10 K Schmitt Trigger The NMI input is a higher priority input than the Input, Active maskable interrupts. It is always recognized at the Low end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the CPU. 3.3 V supply input pin. NC Reserved--No Connection.
58
NMI
59 60
VCC Reserved
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
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Onboard Component Description
Logic-Level I/Os
The I/O connector features 32 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80F91 dual modes, please refer to the eZ80F91 Product Specification (PS0192).
Onboard Battery Backup
An onboard Panasonic VL-1220-1VC 3V Lithium battery powers the 32kHz RealTime Clock when external power is removed. The battery is charged through diode CR1 and resistor R28 when external power is applied to the board.
Ethernet PHY and RJ45 Connector
The eZ80F91 Ethernet Module contains Advanced Micro Devices' Am79C874 Media-Independent Interface (MII) and a HALO RJ45 with integrated magnetics (transformer and common-mode chokes) and two LED indicators. The MII enables different modes of Ethernet communication, configurable by resistors R19, R21, R23, and R24. The eZ80F91 Ethernet Module is shipped with all four resistors installed. Table 4, which lists the available resistor settings, is excerpted from the Am79C874 data sheet published by AMD.
Table 4. eZ80F91 Ethernet Module MII Resistor Configuration R24 ANEG IN IN IN R19 R23 R21 (Tech[2]) (Tech[1]) (Tech[0]) Speed IN IN IN IN IN OUT IN OUT IN Yes1 No No FullDuplex Yes1 No No ANEG-EN Capabilities No No No All 10HD 100HD ANEG Disabled Disabled Disabled
Notes: 1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link. 2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY. 3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should always be enabled.
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Table 4. eZ80F91 Ethernet Module MII Resistor Configuration (Continued) R24 ANEG IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT R19 R23 R21 (Tech[2]) (Tech[1]) (Tech[0]) Speed IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT No Yes1 No No No Yes2 Yes2 Yes2 Yes2 Yes2 Yes2 Yes2 Yes3 FullDuplex No Yes1 No No No Yes2 Yes2 Yes2 Yes2 Yes2 Yes2 Yes2 Yes2 ANEG-EN Capabilities No No No No No Yes3 Yes3 Yes3 Yes3 Yes3 Yes3 Yes3 Yes3 100HD All 10FD 100FD 100FD None 10HD 100HD 100HD, 10HD None 10FD/HD 100FD/HD All ANEG Disabled Disabled Disabled Disabled Disabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled
Notes: 1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link. 2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY. 3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should always be enabled.
Ethernet LEDs
The Ethernet connection is provided by the HALO RJ45 connector. It contains two green LEDs that are located next to each other on the eZ80F91 Module. When PHY is receiving data, the left LED is on. When the PHY is transmitting data, the right LED is on.
Fast Buffer (U10)
The eZ80F91 Module's fast buffer (see Figure 1 on page 3) exists to prevent bus contention that will occur because of slow turn-off time of the module's external Flash and the fast bus turn-around time of the eZ80F91 (generic feature of the eZ80(R) family when it is used in native mode). Below is a short explanation of the problem related to bus contention when using eZ80 family of the microprocessors in native eZ80(R) mode. Refer to Figure 4 on
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page 15 while reading the following discussion. Also see the eZ80F91 Product Specification (PS0192) for further details. Bus contention occurs when two or more devices drive a common bus. The eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High a maximum of 8.8 ns after the next rising edge of the Clock (T6, Figure 4). The Flash turn-off time (TOD) is 25 ns, which is the time from OE or CE going High to the Flash output drivers going into High-Z mode. In other words, after the end of the eZ80F91 Read access to Flash, it takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the eZ80F91 device is already well into the next bus cycle. Assume that the next cycle is Memory Write. During the Memory Write cycle, Data (output) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the Rising edge if Clock is 50 MHz). It means that during TCON = (33.8 ns - 7.5 ns) = 26.3 ns; two devices drive the common Data Bus--the eZ80F91 device and Flash. In turn, data that is being written during the Write operation might be corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns part of the TCON to 5.5 ns. As a result, bus contention still occurs, but its duration is not 26.3 ns, as the following equation shows:
Time of contention = (8.8 ns - 7.5 ns + 5.5 ns) = 6.8 ns
Data being written is not corrupted because the Write pulse is not yet asserted.
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Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature
Memory
The eZ80F91 Module contains external Flash memory, and the eZ80F91 MCU contains internal Flash memory. To allow Read/Write access to Flash memory on the eZ80F91 Module, there are two signals provided, on connectors JP1 and JP2. A jumper JP3 on the module enables programming of on-chip Flash. There is also a signal that duplicates the function of this jumper. Table 5 describes the states of the signals and the status of the jumper for different modes.
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EZ80F915050MOD eZ80F91 Module Product Specification
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Table 5. Flash Memory Programming Signals and Jumpers Signal/Jumper DIS_FLASH FlashWE JP3 F91_WE Function State/Status
Controls Read/Write access to eZ80F91 Module external Flash When Low, access memory is enabled Controls Write operations to the boot block of eZ80F91 Module When Low, Write is external Flash memory enabled Controls Write access to eZ80F91 MCU on-chip Flash memory When IN, Write is enabled Controls Write access to eZ80F91 MCU on-chip Flash memory When Low, Write is enabled
The eZ80F91 Module's external Flash memory has an access time of 100 ns. At least five wait states must be added to the cycle when accessing external Flash at the 50MHz clock speed. eZ80F91 MCU on-chip Flash is faster; its minimum access time is 60 ns, which requires only three wait states at 50 MHz. There is 512 KB of fast SRAM on the eZ80F91 Module. Access time is 12 ns, which requires one wait-state access. The eZ80F91 on-chip SRAM can be used with zero wait states.
IrDA Transceiver
An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1. The receiver supply current is 90-150 A and the transmitter supply current is 260 mA when the LED is active.The IrDA transceiver is accessible via the IrDA controller attached to UART0 on the eZ80F91 device. The UART0 console and the IrDA transceiver cannot be used simultaneously. To use the UART0 for console or to save power, the transceiver can be disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below
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EZ80F915050MOD eZ80F91 Module Product Specification
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2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80F91 Module with a low-impedance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The CPU contains two UARTs with programmable baud rate generators. UART0 is connected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO PC[0:7] on the I/O connector. Note: Do not connect an RS-232 interface without level shifters. There are no RS232-level shifters on the eZ80F91 Module.
Physical Dimensions
The footprint of the eZ80F91 Module PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 5.
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EZ80F915050MOD eZ80F91 Module Product Specification
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16.5 mm 56.0 mm
JP1 1 2
eZ80F91 MODULE R15 R23 R16 R24 R25 U6 + R14 R21 R13 R19 R28
JP2
1
Y1
P2 JP3 ISO U8
R17 R18 R36 R22 R20
CR1
VL1
ZiLOG PCA: 99C0879-001 COPYRIGHT ZiLOG XTOOLS 2002 Y2
78.7 mm
C21
C20
C19
C18
C40
U5 C22 U4 R37 U1
Y3 C12 C11 R6 C42 R4
R3 U2 C1 R29
C3 R10
U3
31.8 mm 63.5 mm
Figure 5. Physical Dimensions of the eZ80F91 Module
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Figure 6 illustrates the top layer silkscreen of the eZ80F91 Module.
JP1 1 2
eZ80F91 MODULE
R15 R23 Y1 R16 R24 R25 U6 + COPYRIGHT ZiLOG XTOOLS 2002 ZiLOG PCA: 99C0879-001 R14 R21 R13 R19 R28
JP2
1
P2 JP3
R17 R18 R36 ISO R22 R20 U8 VL1
CR1
Y2 C18 C21 C20 C19
C40
U5 C22 U4 R37 U1
Y3 C12 C11 R4
R3
C3 R10
R6 C42
U2 C1 R29 U3
Figure 6. eZ80F91 Module--Top Layer
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Figure 7 illustrates the bottom layer silkscreen of the eZ80F91 Module.
JP2 DJP 2002 1 C4
R35
R34 2
JP1
C7 C16 C13
C14 C39 C51 C50 C49 C48 C47 C34 C35 C26 L1 C27 C36 C25 C33 C29 U9 R11 R31 C17 C44 C45 C46 R33 R32 C15 C52 C53
C9 C38 R27 C8 C10 R9 C24 C5 R26 R8 R7 R2 R1 R30 R12 R5 C6 C37
C32
C30
C31
C28
C23 U10
C43
C41
C2
MADE IN U.S.A. ZiLOG FAB: 98C0879-001 REV A
Figure 7. eZ80F91 Module--Bottom Layer
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS).
Table 6. Absolute Maximum Ratings Parameter Standard operating temperature Storage temperature Operating Humidity (RH @ 50C) Operating Voltage Min 0 -45 25% -- Max +70 +85 90% 3.6 V Units C C
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Document Number Description
The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table:
PS 0193 10 0904 Product Specification Unique Document Number Revision Number Month and Year Published
Change Log
Rev 01 02 03 04 05 06 07 08 09 10 Date December 2002 January 2003 February 2003 June 2003 June 2003 August 2003 December 2003 December 2003 March 2004 Purpose Original issue Minor content revision Minor content revision Minor content revision Minor content revision Hyperlink correction Typo correction Correction to BOM Correction to schematic
September 2004 Corrections to PHY section
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Module Bill of Materials
Table 7 lists the installed components of the eZ80F91 Module.
Table 7. Bill of Materials for the eZ80F91 Module Part Number 98C0879-001 35-0180-12 35-0016-05 35-0720-10 35-0719-00 ZHX1810 35-0062-01 35-0022-01 eZ80F91 35-0731-00 48-1013-01 17-2005-70 17-2005-66 Part Name Fab, eZ80F91 Module, Rev. B IC, SRAM, 512Kx8, 12ns, 3V, 36-SOJ IC, 74LVC04, 3.3V, GATE, 14-SOIC IC, Flash, 1Mx8, 100ns, 3V, 40-TSSOP IC, MAX6328, RESET, SOT-23 IC, IR Transceiver, Low Profile IC, 74LCX32, LV, QUAD OR, 14-TSSOP IC, AM7C874, PHY XCVR, 80QFP IC, eZ80F91, 50MHZ, 144VQFP IC, 74CBTLV3861PWR, 24-TSSOP Diode, TVS Array, XCVR Prot, 8-SOIC CAP, 1000 pF, 50 V, Ceramic Chip, 0603 CAP, 0.1 F, 16 V, Ceramic Chip, 0603 Qty. 1 1 1 1 1 1 1 1 1 1 1 15 28 Jumper Location Manufacturer -- U8 U1 U9 U3 U2 U4 U6 U5 U10 U9 Prime Technologies Alliance Semi. AS7C34096-12JC Texas Instruments SN74LVC04AD Micron Technologies MT28F008B3VG-10B Maxim Inc. MAX6328UR29-T ZiLOG Inc. ZHX1810MV115THTR Fairchild Semi. 74LCX32MTC AMD AM79C874VC ZiLOG Inc. eZ80F91 Texas Instruments SN74CBTLV3861PWR Semtec LCDA15C-6
C13, C14, Panasonic C31-43 ECJ-1VC1H561J C2,10, C15-30, C44-53 C3 C1 C6 Kemet Inc. C0603C104K5RAC Panasonic ECJ-1VB1C103K Panasonic ECJ-1VF1C334Z Panasonic ECJ-1VC1H563K
17-2005-54 17-2005-83 17-2005-63
CAP, 0.01 F, 50 V, Ceramic Chip, 0603 CAP, 0.33 F, 16 V, Ceramic Chip, 0603 CAP, 560 pF, 50 V, Ceramic Chip, 0603
1 1 1
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Table 7. Bill of Materials for the eZ80F91 Module (Continued) Part Number 17-2001-03 17-2001-05 17-2001-20 17-2001-01 48-0051-00 16-9005-33 46-3001-03 Part Name CAP, 12 pF, 50 V, Ceramic Chip, 0603 CAP, 22PF, 50V, CER CHIP, 0603 CAP, 270PF, 50V, CER CHIP, 0603 CAP, 5PF, 50V, CER CHIP, 0603 DIODE, 1N5817, RCTFR INDUCTOR, 3.3 H, 20%, 1210 SMD Resistor, 10 K, 1%, 1/16 W, 0603 SMT Qty. 4 2 1 1 1 1 15 Jumper Location Manufacturer C9, C11, Panasonic C12 ECJ-1VC1H120J C4, C7 C5 C8 CR1 L1 PANASONIC ECJ-1VC1H220J PANASONIC ECJ-1VC1H271J PANASONIC ECJ-1VC1H050C MOTOROLA 1N5817 PANASONIC ELJ-PA3R3MF
R3, 8, 10, Sprague R12-18, 420CK472X2PD R20, 25, 29, 30, 37 R19, 21, 23, 24 R5, R6 R3 R4 R11, 31, 32, 33 R22 R26 R27 R28 R34, R35 R38 Y1 Y2 " " " " " " " " " " " CITIZEN HC49US25.000MABJ CITIZEN HC49US50.000MABJ
46-3000-00 46-3000-71 46-3000-35 46-3000-02 46-3000-32 46-3000-63 46-3000-56 46-3001-34 46-3000-47 46-3000-51 46-3001-75 23-0000-25 23-0000-50
Resistor, 0 , 1%, 1/16 W, 0603 SMT Resistor, 2.21 K, 1%, 1/16W, 0603 SMT Resistor, 68 , 1%, 1/16 W, 0603 SMT RES, 2.2 , 1%, 1/16W, 0603 SMT RES, 49.9 , 1%, 1/16W, 0603 SMT RES, 1 K, 1%, 1/16W, 0603 SMT RES, 499 ,1%, 1/16W, 0603 SMT RES, 200 K, 1%, 1/16W, 0603 SMT RES, 221 , 1%, 1/16W, 0603 SMT RES, 332 , 1%, 1/16W, 0603 SMT RES, 10 M, 1%, 1/16W, 0603 SMT XTAL, 25.0000 MHz, SER/RESN, HC49S XTAL, 50.0000 MHz, SER/RESN, HC49S
4 2 1 1 4 1 1 1 1 2 1 1 1
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Table 7. Bill of Materials for the eZ80F91 Module (Continued) Part Number 23-0006-00 21-0907-01 21-0055-02 Part Name Internal crystal, 32.768 KHz, SER/RESN, TF case Connector, RJ45, Fast jack,10/100 Base-T Connector, HDR/PIN, .025SQ, double row Qty. 1 1 2 Jumper Location Manufacturer Y3 P2 Fox NC-38 Halo Electronics HFJ11-2450E-L11
JP1, JP2 Harwin (backside) M-20-976-3622
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EZ80F915050MOD eZ80F91 Module Product Specification
Schematics
Figures 8 through 10 diagram the layout of the eZ80F91 Module. Ethernet circuiting devices are not loaded on the eZ80F91 Module. However, these devices appear in the following schematics for reference purposes.
VCC VCC A[0..23] D[0..7] -CS[0..3] IICSDA IICSCL CLK_OUT -DIS_FLASH A[0..23] D[0..7] -CS[0..3] IICSDA IICSCL CLK_OUT -DIS_FLASH EZ80CLK JP3 1 2 -FLASHWE RTC_VDD PA[0..7] PB[0..7] PC[0..7] PD[0..7] -RESET -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI -FLASHWE RTC_VDD PA[0..7] PB[0..7] PC[0..7] PD[0..7] VCC -RESET -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI R7 10K R8 10K TDI TDO TRIGOUT TCK TMS -TRSTN R9 4.7K VCC 74LCX04 TSSOP14 GND R12 10K U1C -DIS_IRDA 5 74LCX04 TSSOP14 6 DISABLE_IRDA PD2 = IR_SD U4B 4 6 5 74LCX32 TSSOP14 IRDA_SD C2 0.1F GND 3 VCC U3 R10 10K -RESET VCC U1B TDI TDO TRIGOUT TCK TMS -TRSTN R20 10K 1 3 74LCX04 TSSOP14 U1F 12 13 12 13 74LCX32 TSSOP14 11 4 2 74LCX32 TSSOP14 U4D VCC 3 U4A -WAIT HEADER 30x2/SM -BUSREQ VCC VCC HEADER 30x2/SM R5 2.2K R6 2.2K R1 4.7K R2 4.7K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 A21 37 A22 39 -CS0 41 -CS2 43 D1 45 D3 47 D5 49 D7 51 -MREQ 53 GND 55 -WR 57 -BUSACK 59 -TRSTN -F91_WE GND A6 A10 GND A8 A13 A15 A18 A19 A2 A11 A4 A5
25
Connector 1
JP1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 IICSDA IICSCL
Connector 2
JP2 PA7 1 PA5 3 PA3 5 PA1 7 VCC 9 PB7 11 PB5 13 PB3 15 PB1 17 GND 19 PC6 21 PC4 23 PC2 25 PC0 27 PD6 29 PD5 31 PD3 33 PD1 35 TDO 37 GND 39 TCK 41 RTC_VDD 43 IICSCL 45 IICSDA 47 -FLASHWE 49 -CS3 51 -RESET 53 VCC 55 -HALT_SLP 57 VCC 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PA6 PA4 PA2 PA0 GND PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK GND -DIS_IRDA -WAIT GND -NMI
U1A -F91_WE 1 74LCX04 TSSOP14 2 -F91_WP -F91_WP
R37 10K
WR_EN
VCC A0 A3 VCC A7 A9 A14 A16 GND A1 A12 A20 A17 -DIS_FLASH VCC A23 -CS1 D0 D2 D4 GND D6 -IOREQ -RD -INSTRD -BUSREQ
VCC R3 C1
R4 2R7
68R
330nF U2 5 VCC LEDA TXD SD RXD GND T ZHX1810 0
(MMA 02 04) PD0 IRDA_SD PD1
1 2 4 3 6
VDD
GND
RESET
2
open-drain
C3 0.01F
MAX6328UR29 SOT-23-L3
VCC
alternative: Maxim MAX6802UR29D3
VCC GND GND
VCC
GND
Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3--Connectors and Miscellaneous
PS019310-0904 PRELIMINARY Schematics
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EZ80F915050MOD eZ80F91 Module Product Specification
26
D[0:7] D0 D1 D2 D3 D4 D5 D6 D7 -WAIT -BUSREQ -NMI TMS TCK TDI -TRSTN -RESET -F91_WP -WAIT -BUSREQ -NMI TMS TCK TDI -TRSTN -RESET -F91_WP CRS COL RXER RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXCLK 39 40 41 42 43 44 45 46 54 57 56 66 67 69 71 55 144 124 125 135 137 141 140 139 138 136 131 83 Y2 50MHz R27 85 86
U5 D0 D1 D2 D3 D4 D5 D6 D7 WAIT BUSREQ NMI TMS TCK TDI TRSTN RESET WP MII_CRS MII_COL MII_RXER MII_RXDV MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXCLK MII_TXCLK FILT_IN XOUT XIN A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXEN MII_TXER MII_MDC MII_MDIO IORQ MRQ RD WR BUSACK CS0 CS1 CS2 CS3 SCL SDA VDD VDD VDD VDD VDD VDD VDD PLL_VDD VDD VDD VDD VDD VDD PA7_PWM3 PA6_PWM2_EC1 PA5_PWM1_TOUT1 PA4_PWM0_TOUT0 PA3_PWM3_OC3 PA2_PWM2_OC2 PA1_PWM1_OC1 PA0_PWM0_OC0 PB7_MOSI PB6_MISO PB4_ICB3 PB4_ICA3 PB3_SCK PB2_SS PB0_IC1 PB0_IC0_EC0 PC7_RI1 PC6_DCD1 PC5_DSR1 PC4_DTR1 PC3_CTS1 PC2_RTS1 PC1_RXD1 PC0_TXD1 PD7_RI0 PD6_DCD0 PD5_DSR0 PD4_DTR0 PD3_CTS0 PD2_RTS0 PD1_RXD0_IRRXD PD0_TXD0_IRTXD HALT_SLP PHI INSTRD TDO TRIGOUT EZ80F91 1 2 3 4 5 8 9 10 11 12 13 16 17 18 19 20 21 24 25 26 27 28 29 30 126 127 128 129 130 132 142 143 49 50 51 52 58 33 34 35 36 110 109 121 120 119 118 117 116 115 114 107 106 105 104 103 102 101 100 97 96 95 94 93 92 91 90 80 79 78 77 76 75 74 73 65 111 53 70 68 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 TXD3 TXD2 TXD1 TXD0 TXEN TXER MDC MDI0 -IORQ -MREQ -RD -WR -CS0 -CS1 -CS2 -CS3 SCL SDA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 -IORQ -MREQ -RD -WR -BUSACK -CS0 -CS1 -CS2 -CS3 IICSCL IICSDA
A[0:23]
GND VCC R18 10K U6 1 2 3 5 7 8 9 14 15 16 17 18 19 20 21 22 30 23 24 25 26 29 31 33 40 39 38 37 34 32 41 42 PCSB ISODEF ISO REFCLK BURN_IN RST PWRDN PHYAD4_0RXDPHYAD3_10RXD+ PHYAD2_10TXD++ PHYAD1_10TXDPHYAD0_10TXD-GPIO0_10TXD-GPIO1_TP125 MDIO MDC RXCLK RXD3 RXD2 RXD1 RXD0 RXDV RXER_RXD4 TXCLK_PCSBPCLK TXD3 TXD2 TXD1 TXD0 TGND1 PLLGND OGND1 DGND1 DGND2 OGND2 CRVGND EQGND REFGND TGND2 TXEN TXER_TXD4 COL CRS AM79C874 10 13 27 36 49 52 59 60 73 79 80 VCC R19 INTR TECH_SEL2 TECH_SEL1 TECH_SEL0 ANEGA IBREF RPTR LEDSPD0_LEDBTA_FXSEL LECOL_SCRAMEN LEDRX_LEDSEL LEDTX_LEDBTB LEDLNK_LED_10LNK LESPD1_LEDTXA_CLK25EN LEDDPX_LEDTXB TEST3_SDI+ TEST2 TEST1_FXR+ TEST0_FXRFXT+ FXTXTLXTL+ TX+ TXRX+ RX43 53 54 55 56 72 61 44 45 46 47 48 57 58 62 68 67 66 69 70 74 75 77 78 64 63 C4 18pF -LEDLNK -LEDRX R25 10K R23 R21 R24 0 0 0 0 R13 10K R14 10K R15 10K R16 10K R17 10K 0.1%
-RESET R22 1K GND
MDI0 MDC RXCLK RXD3 RXD2 RXD1 RXD0 RXDV RXER TXCLK TXD3 TXD2 TXD1 TXD0 TXEN TXER COL CRS
C6 GND
0.056F C5 220pF
R26 499
PLLVCC OVDD1 VDD1 VDD2 OVDD2 CRVVCC ADOVCC EQVCC REFVCC TVCC1 TVCC2
Y1 25 MHz C7 18pF GND VCC C17 0.1F
L1 3.3H
200K C8 C9 10pF 5pF
C10 0.1F VCC RTC_VDD VCC 2 CR1 1N5817 1 RTC_VDD
6 14 22 31 47 59 81 87 88 98 112 122 133
4 11 12 28 35 50 51 65 71 76
R11 49.9 GND VCC C44 0.1F C45 0.1F C46 0.1F C47 0.1F C48 0.1F VCC R32 R31 49.9 R34 330 R35 330 R33 49.9 C15 0.1F C16 0.1F 9 10 11 12 -LEDRX -LEDLNK 49.9 1 4 2 3 5 6 8
P2 TX+ TXCT TXRX+ RXCT RXGND AN1 CT1 AN2 CT2 HFJ11-2450E-L11
PA[0:7]
C49 0.1F
C50 0.1F GND
C51 0.1F
C52 0.1F
C53 0.1F
Put caps between pairs of U6, 10:11, 51:52, 59:65 and 71:73 as close to the pins as possible
R28 220
Y3 32.768KHz VL1 R38 10M
7 15 23 32 38 48 60 64 72 82 84 89 99 108 113 123 134 63 62 61 C12 12pF
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PLL_VSS VSS VSS VSS VSS VSS VSS RTC_VDD RTC_XOUT RTC_XIN
PB[0:7]
VCC
PC[0:7]
C31 0.001F
C32 0.001F
C33 0.001F
C34 0.001F
C35 0.001F
C36 0.001F
C37 0.001F
C38 0.001F
C39 0.001F
C40 0.001F
C41 0.001F
C42 0.001F
C43 0.001F GND C30 0.1F VCC
C18 0.1F
C19 0.1F
C20 0.1F
C21 0.1F
C22 0.1F
C23 0.1F
C24 0.1F
C25 0.1F
C26 0.1F
C27 0.1F
C28 0.1F
C29 0.1F
C11 12pF GND
PD[0:7] -HALT_SLP CLK_OUT -INSTRD TDO TRIGOUT
VCC
VCC GND
VCC GND
GND
Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3--CPU and PHY
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Schematics
EZ80F915050MOD eZ80F91 Module Product Specification
27
U8 A18 A0 A1 A2 A3 -CS1 D0 D1 D2 D3 -WR A12 A9 A6 A4 A17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 N.C. A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A16 A15 A14 A13 -RD D7 D6 D5 D4 A11 A8 A10 A7 A5
-CS1
-CS1 VCC VCC
VCC
C13 0.001uF
512KB x 8 SRAM SOJ36.400 D[0:7] VCC
A[0:23]
U9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VCC 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
30 31
A[0..23]
A[0..23]
VDD VDD
U10 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE OE WE RP WP VPP 25 26 27 28 32 33 34 35 22 24 9 10 12 11 29 38 A21 A20 DFLASH0 DFLASH1 DFLASH2 DFLASH3 DFLASH4 DFLASH5 DFLASH6 DFLASH7 -CSFLASH -RD -WR -RESET -WP VCC 2 5 6 9 10 15 16 19 20 23 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 1OE 2OE 74CBTLV3384 SO24.300 3 4 7 8 11 14 17 18 21 22 1 13 D0 D1 D2 D3 D4 D5 D6 D7
VCC
C14 0.001F
-CSFLASH
VSS VSS 23 39
N.C. N.C.
Flash 1Mx8 3.3V TSOP40.20MM MT28F008B3VG U4C -CS0 8 -FLASH_EN 9 8 10 74LCX32 TSSOP14 -CSFLASH
R29 10K -DIS_FLASH -RD -WR -CS0 -DIS_FLASH -RD -WR -CS0 9
U1D
74LCX04 TSSOP14 VCC
VCC VCC
-RESET -FLASHWE
-RESET -FLASHWE
R30 10K
GND U1E GND 10 -WP
11
74LCX04 TSSOP14
Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3--Module Memory
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EZ80F915050MOD eZ80F91 Module Product Specification
28
Customer Feedback Form
The eZ80F91 Module Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information
Name Company Address City/State/Zip Country Phone Fax Email
Product Information
Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type
Return Information
ZiLOG System Test/Customer Support 532 Race Street San Jose, CA 95126 Phone: (408) 558-8500 Fax: (408) 558-8536 ZiLOG Customer Support
Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary.
_____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________
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